This application claims the benefit of U.S. Provisional Patent Application No. 61/790,182, filed Mar. 15, 2013, which is expressly incorporated by reference herein in its entirety.
Integrated circuits (ICs) are created by patterning a substrate and materials deposited on the substrate or semiconductor wafer. The patterned features generally comprise devices and interconnections. Processes for creating an IC generally commence by a designer hierarchically defining functional components of a circuit using hardware description language. From this high-level functional description, a physical circuit implementation dataset is created describing cell-to-cell connectivity. Using this dataset, a layout file is created through a placing and routing process assigning logic cells to physical locations in the device layout and routing their respective interconnections. Component devices and interconnections of the IC are then constructed or processed layer by layer.
With a continuing desire to provide greater functionality in smaller packages and the evolution of system-on-chip and mixed-signal designs, IC feature geometries are being driven to smaller and smaller dimensions. One class of technologies used to enhance feature density is referred to as multiple patterning and/or double patterning There are several types of double patterning in use, including: litho-etch -litho-etch (LELE); litho-freeze-litho-etch (LFLE); self-aligned double patterning (SADP), also known as spacer-assisted double patterning, or sidewall image transfer (SIT). Such techniques can be used to enhance feature density; however, there are limitations to these techniques.